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features ? 16-channel gps correlator ? 8192 search bins with gps acquisition accelerator ? accuracy: 2.5m cep (stand-alone, s/a off) ? time to first fix: 34s (cold start) ? acquisition sensitivity: ?142 dbm ? tracking sensitivity: ?158 dbm utilizes the arm7tdmi ? arm ? thumb ? processor core ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? embedded ice (in-circuit emulator) 128 kbyte internal ram 384 kbyte internal rom with u-blox gps firmware 6-channel peripheral data controller (pdc) 8-level priority, individually maska ble, vectored interrupt controller ? 2 external interrupts 24 user-programmable i/o lines 1 usb device port ? universal serial bus (u sb) v2.0 full-speed device ? embedded usb v2.0 full-speed transceiver ? suspend/resume logic ? ping-pong mode for isochronous and bulk endpoints 2 usarts ? 2 dedicated peripheral data cont roller (pdc) channels per usart master/slave spi interface ? 2 dedicated peripheral data controller (pdc) channels ? 8-bit to 16-bit prog rammable data length ? 4 external slave chip selects programmable watchdog timer advanced power management controller (apmc) ? peripherals can be d eactivated individually ? geared master clock to reduce power consumption ? sleep state with disabled master clock ? hibernate state with 32.768 khz master clock real time clock (rtc) 2.3v to 3.6v or 1.8v core supply voltage includes power supervisor 1.8v to 3.3v user-definable i/o voltag e for several gpios with 5v tolerance 4 kbytes battery backup memory 8 mm 8 mm 56 pin qfn56 package pb-free, rohs-compliant, green gps baseband processor supersense atr0625 preliminary rev. 4925a?gps?02/06
2 4925a?gps?02/06 atr0625 [preliminary] 1. description the gps baseband processor atr0625 includes a 16-channel gps correlator and is based on the arm7tdmi ? processor core. this processor has a high-performance 32-bit ri sc architecture and very low power con- sumption. in addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. the atr0625 has two usart and an usb device port. this port is compliant with the universal serial bus (usb) v2.0 full-speed device specification. the atr0625 includes full gps supersense ? firmware, licensed from u-blox ag, which per- forms the basic gps operation, including tracking, acquisition, navigation and position data output. for normal pvt (position/velocity/time) applications, there is no need for off-chip flash memory or rom. the firmware supports the possibility to store the configuration set- tings in an optional external eeprom. for customer-specific appli cations, a software development kit is available. the atr0625 is manufactured using atmel?s hi gh-density cmos technology. by combining the arm7tdmi microcontroller core with on-chip sram, 16-channel gps correlator, and a wide range of peripheral functions on a monolithic chip, the atr0625 provides a highly flexible and cost-effective solution for gps applications.
3 4925a?gps?02/06 atr0625 [preliminary] figure 1-1. atr0625 block diagram nsleep nshdn xt_in nreset tms tck tdo tdi ntrst dbg_en clk23 rf_on p0/nantshort p15/anton p31/rxd1 p18/txd1 p22/rxd2 p21/txd2 p2/boot_mode p16/neeprom p8/statusled p30/agcout0 ldo_en ldo_in ldo_out ldobat_in vbat p1/gpsmode0 p12/gpsmode2 p13/gpsmode3 p17/gpsmode5 p23/gpsmode7 p24/gpsmode8 p26/gpsmode10 p27/gpsmode11 p29/gpsmode12 p19/gpsmode6 p25/naadet0 p14/naadet1 p9/extint0 sighi0 siglo0 vbat18 xt_out p20/timepulse usb_dm usb_dp embedded ice arm7tdmi usart1 usart2 pio2 spi usb asb apb pdc2 b r i d g e rom 384k usb transceiver sram 128k power supply manager watchdog jtag pio2 reset controller interface to off-chip memory (ebi) advanced interrupt controller gps accelerator timer counter gps correlators smd generator advanced power manage- ment controller sram rtc pio2 controller special function
4 4925a?gps?02/06 atr0625 [preliminary] 2. architectural overview 2.1 description the atr0625 architecture consis ts of two main buse s, the advanced s ystem bus (asb) and the advanced peripheral bus (apb). the asb is de signed for maximum pe rformance. it inter- faces the processor with the on-chip 32-bit me mories. the apb is designed for accesses to on-chip peripherals and is optimized for low power consumption. the amba ? bridge provides an interface between the asb and the apb. an on-chip peripheral data controller (pdc2) transfers data between the on-chip usarts/spi and the on-chip and off-chip memori es without processor intervention. most importantly, the pdc2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. it can transfer up to 64k con- tiguous bytes without reprogramming the starting address. as a result, the performance of the microcontroller is increased and the power consumption reduced. the atr0625 peripherals are designed to be easily programmable with a minimum number of instructions. each peripheral has a 16 kbyte address space allocated in the upper 3 mbyte of the 4 gbyte address space. (except for the interrupt controller, which has 4 kbyte address space.) the peripheral base address is the lowe st address of its memory space. the periph- eral register set is composed of control, mode, data, status, and interrupt registers. to maximize the efficiency of bit manipulati on, frequently written registers are mapped into three memory locations. the first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. a bit can be set or reset by writing a ?1? to the corresponding position at the appropriate address. writing a ?0? has no effect. individual bits can thus be modi fied without having to use costly read-modify- write and complex bit-manipulation instructions. all of the external signals of the on-chip peri pherals are under the control of the parallel i/o (pio2) controller. the pio2 controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. after reset, the user must carefully program the pio2 controller in order to define which peripheral signals are connected with off-chip logic. the arm7tdmi ? processor operates in little-endian mode on the atr0625 gps baseband. the processor's internal architecture and the arm ? and thumb ? instruction sets are described in the arm7tdmi datasheet. the memory map and the on-chip peripherals are described in detail in the atr0625 full datashe et. the electrical and mechanical characteris- tics are also documented in the atr0625 full datasheet. the arm standard in-circuit emulator (ice) debug interface is supported via the jtag/ice port of the atr0625. for features of the rom firmware, refer to the software documentation available from u-blox ag, switzerland.
5 4925a?gps?02/06 atr0625 [preliminary] 3. pin configuration 3.1 pinout figure 3-1. pinout qfn56 (top view) 42 29 114 43 28 56 15 atr0625 table 3-1. atr0625 pinout pin name qfn56 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b ioio clk23 37 in dbg_en 8 in pd gnd (2) in ldobat_in 21 in ldo_en 25 in ldo_in 20 in ldo_out 19 out nreset 41 i/o open drain pu nshdn 26 out nsleep 24 out ntrst 13 in pd p0 40 i/o pd nantshort p1 47 i/o configurable (pd) gpsmode0 agcout1 p2 46 i/o configurable (pd) boot_mode ?0? p8 48 i/o configurable (pd) statusled ?0? p9 29 i/o pu extint0 extint0 p12 49 i/o configurable (pu) gpsmode2 npcs2 p13 32 i/o pu gpsmode3 extint1 notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. ground plane 3. vbat18 represent the internal power supply of the backup power domain, see section ?power supply? on page 17 . 4. vddio is the supply voltage for the following gpio-pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29, see section ?power supply? on page 17 . 5. vdd_usb is the supply voltage for following the usb-pins: usb_dm and usb_dp, see section ?power supply? on page 17 . for operation of the usb interface, supply of 3.0v to 3.6v is required. 6. this pin is not connected
6 4925a?gps?02/06 atr0625 [preliminary] p14 1 i/o configurable (pd) naadet1 ?0? p15 17 i/o pd anton p16 6 i/o configurable (pu) neeprom sighi1 nwd_ovf p17 2 i/o configurable (pd) gpsmode5 sck1 sck1 p18 45 i/o configurable (pu) txd1 txd1 ?0? p19 53 i/o configurable (pu) gpsmode6 siglo1 ?0? p20 4 i/o configurable (pd) timepulse sck2 sck2 timepulse p21 52 i/o configurable (pu) txd2 txd2 ?0? p22 30 i/o pu rxd2 rxd2 p23 3 i/o configurable (pu) gpsmode7 sck sck mclk_out p24 5 i/o configurable (pu) gpsmode8 mosi mosi ?0? p25 55 i/o configurable (pd) naadet0 miso miso ?0? p26 44 i/o configurable (pu) gpsmode10 nss npcs0 ?0? p27 54 i/o configurable (pu) gpsmode11 npcs1 p29 50 i/o configurable (pu) gpsmode12 npcs3 p30 16 i/o pd agcout0 agcout0 ?0? p31 31 i/o pu rxd1 rxd1 rf_on 15 out pd sighi0 38 in siglo0 39 in tck 9 in pu tdi 10 in pu tdo 11 out tms 12 in pu usb_dm 34 i/o usb_dp 35 i/o vbat 22 in vbat18 (3) 23 out vdd18 7, 14 in vdd18 18, 36 in vdd18 51 in vddio (4) 43, 56 in vdd_usb (5) 33 in xt_in 28 in xt_out 27 out nc (6) 42 table 3-1. atr0625 pinout (continued) pin name qfn56 pin type pull resistor (reset value) (1) firmware label pio bank a pio bank b ioio notes: 1. pd = internal pull-down resistor, pu = internal pull-up resistor, oh = switched to output high at reset 2. ground plane 3. vbat18 represent the internal power supply of the backup power domain, see section ?power supply? on page 17 . 4. vddio is the supply voltage for the following gpio-pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p26, p27 and p29, see section ?power supply? on page 17 . 5. vdd_usb is the supply voltage for following the usb-pins: usb_dm and usb_dp, see section ?power supply? on page 17 . for operation of the usb interface, supply of 3.0v to 3.6v is required. 6. this pin is not connected
7 4925a?gps?02/06 atr0625 [preliminary] 3.2 signal description table 3-2. atr0625 signal description module name function type active level comment ebi boot_mode boot mode input input ? pio-controlled after reset, internal pull-down resistor usart txd1 to txd2 transmit data output output ? pio-controlled after reset rxd1 to rxd2 receive data input input ? pio-controlled after reset sck1 to sck2 external synchronous seri al clock i/o ? pio-controlled after reset usb usb_dp usb data (d+) i/o ? usb_dm usb data (d-) i/o ? apmc rf_on output ? interface to atr0601 aic extint0-1 external interrupt request input high/ low/ edge pio-controlled after reset agc agcout0-1 automatic gain control output ? interface to atr0601 pio-controlled after reset rtc nsleep sleep output output low interface to atr0601 nshdn shutdown output output low connect to pin ldo_en xt_in oscillator input input ? rtc oscillator xt_out oscillator output output ? rtc oscillator spi sck spi clock i/o ? pio-controlled after reset mosi master out slave in i/o ? pio-controlled after reset miso master in slave out i/o ? pio-controlled after reset nss/npcs0 slave select i/o low pio-controlled after reset npcs1 to npcs3 slave select output low pio-controlled after reset wd nwd_ovf watchdog timer overflow output ? pio-controlled after reset pio p0 to p31 programmable i/ o port i/o ? input after reset gps sighi0 digital if input ? interface to atr0601 siglo0 digital if input ? interface to atr0601 sighi1 digital if input ? pio-controlled after reset siglo1 digital if input ? pio-controlled after reset timepulse gps synchronized time pulse output ? pio-controlled after reset config gpsmode0-12 gps mode input ? pio-controlled after reset statusled status led output ? pio-controlled after reset neeprom enable eeprom support input low pio-controlled after reset anton active antenna power on output output ? pio-controlled after reset nantshort active antenna short circuit detection input input low pio-controlled after reset naadet0-1 active antenna detection inpu t input low pio-controlled after reset note: 1. the usb transceiver is disabled if vdd_usb < 2.0v. in this case the pins usb_dm and usb_dp are connected to gnd (internal pull-down resistors). the usb transceiver is enabled if vdd_usb is within 3.0v and 3.6v.
8 4925a?gps?02/06 atr0625 [preliminary] jtag/ice tms test mode select input ? internal pull-up resistor tdi test data in input ? internal pull-up resistor tdo test data out output ? tck test clock input ? internal pull-up resistor ntrst test reset input input low internal pull-down resistor dbg_en debug enable input high internal pull-down resistor clock clk23 clock input input ? interface to atr0601, schmitt trigger input mclk_out master clock output ou tput ? pio-controlled after reset reset nreset reset input i/o low open drain with internal pull-up resistor power vdd18 power ? core voltage 1.8v vddio power ? variable io voltage 1.65v to 3.6v vdd_usb power ? usb voltage 0 to 2.0v or 3.0v to 3.6v (1) gnd power ? ground ldobat ldobat_in power ? 2.3v to 3.6v vbat power ? 1.5v to 3.6v vbat18 out ? 1.8v backup voltage ldo18 ldo_in ldo in power ? 2.3v to 3.6v ldo_out ldo out power ? 1.8v core voltage, max. 80 ma ldo_en ldo enable input ? table 3-2. atr0625 signal description (continued) module name function type active level comment note: 1. the usb transceiver is disabled if vdd_usb < 2.0v. in this case the pins usb_dm and usb_dp are connected to gnd (internal pull-down resistors). the usb transceiver is enabled if vdd_usb is within 3.0v and 3.6v.
9 4925a?gps?02/06 atr0625 [preliminary] 3.3 setting gpsmode0 to gpsmode12 the start-up configuration of a rom-based syst em without external non-volatile memory is defined by the status of the gpsmode pins after system reset. alternatively, the system can be configured through message commands passed through the serial interface after start-up. this configuration of the atr0625 can be stored in an external non-volatile memory like eeprom. default designates settings used by rom fi rmware if gpsmode configuration is disabled (gpsmode0 = 0). 3.3.1 enable gpsmode pin configuration if the gpsmode configuration is enabled (gps mode0 = 1) and the other gpsmode pins are not connected externally, the reset default values of the internal pull-down and pull-up resistors will be used. table 3-3. gpsmode functions pin function gpsmode0 (p1) enable configuration with gpsmode pins gpsmode1 (p9) this pin (extint0) is used for fixnow functionality and not used for gpsmode configuration. gpsmode2 (p12) gps sensitivity settings gpsmode3 (p13) gpsmode4 (p14) this pin (naadet1) is used as active antenna supervisor input and not used for gpsmode configuration. this is the def ault selection if gpsmode configuration is disabled. gpsmode5 (p17) serial i/o configuration gpsmode6 (p19) gpsmode7 (p23) usb power mode gpsmode8 (p24) general i/o configuration gpsmode9 (p25) this pin (naadet0) is used as active antenna supervisor input and not used for gpsmode configuration. gpsmode10 (p26) general i/o configuration gpsmode11 (p27) gpsmode12 (p29) serial i/o configuration table 3-4. enable configuration with gpsmode pins gpsmode0 (reset = pd) description 0 ignore all gpsmode pins. the default settings as indicated below are used. 1 use settings as specified with gpsmode[2, 3, 5 to 8, 10 to 12]
10 4925a?gps?02/06 atr0625 [preliminary] 3.3.2 sensitivity settings 3.3.3 serial i/o configuration the atr0625 features a two-stage i/o message and protocol selection procedure for the two available serial ports. at the first stage, a certain protocol can be enabled or disabled for a given usart port or the usb port. selectable protocols are rtcm, nmea and ubx. at the second stage, messages can be enabled or disa bled for each enabled protocol on each port. in all configurations discussed below, all protocols are enabled on all ports. but output mes- sages are enabled in a way that ports appear to communicate at only one protocol. however, each port will accept any input message in any of the three implemented protocols both usart ports and the usb port accept input messages in all three supported protocols (nmea, rtcm and ubx) at the configured baud rate. input messages of all three protocols can be arbitrarily mixed. resp onse to a query input message will always use the same proto- col as the query input message. the usb port does only accept nmea and ubx as input protocol by default. rtcm can be enabled via protocol messages on demand. in auto mode, no output message is sent out by default, but all input messages are accepted at any supported baud rate. again, usb is re stricted to only nmea and ubx protocols. response to query input comman ds will be given the same protoc ol and baud rate as it was used for the query command. using the respective configuration commands, periodic output messages can be enabled. table 3-5. gps sensitivity settings gpsmode3 (fixed pu) gpsmode2 (reset = pu) description 0 0 auto mode 0 1 fast mode 1 0 normal mode (default rom value) 1 1 high sensitivity table 3-6. serial i/o configuration gpsmode12 (reset = pu) gpsmode6 (reset = pu) gpsmode5 (reset = pd) usart1/usb (output protocol/ baud rate (kbaud)) usart2 (output protocol/ baud rate (kbaud)) messages information messages 0 0 0 ubx/57.6 nmea/19.2 high user, notice, warning, error 0 0 1 ubx/38.4 nmea/9.6 medium user, notice, warning, error 0 1 0 ubx/19.2 nmea/4.8 low user, notice, warning, error 0 1 1 ?/auto ?/auto off none 1 0 0 nmea/19.2 ubx/57.6 high user, notice, warning, error 1 0 1 nmea/4.8 ubx/19.2 low user, notice, warning, error 1 1 0 nmea/9.6 ubx/38.4 medium user, notice, warning, error 1 1 1 ubx/115.2 nmea/19.2 debug all
11 4925a?gps?02/06 atr0625 [preliminary] the following message settings are used in the tables below: the following settings apply if gpsmode configuration is not enabled, that is, gpsmode = 0 ( rom-defaults ): table 3-7. supported messages at setting low nmea port standard gga, rmc ubx port nav sol, svinfo mon except table 3-8. supported messages at setting medium nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon except table 3-9. supported messages at setting high nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda, grs, gst proprietary pubx00, pubx03, pubx04 ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon schd, io, ipc, except table 3-10. supported messages at setting debug (additional undocumented message may be part of output data) nmea port standard gga, rmc, gsa, gsv, gll, vtg, zda, grs, gst proprietary pubx00, pubx03, pubx04 ubx port nav sol, svinfo, posecef, posllh, status, dop, velecef, velned, timegps, timeutc, clock mon schd, io, ipc, except rxm raw (raw message support requires an additional license) table 3-11. serial i/o default setting if gpsm ode configuration is deselected (gpsmode0 = 0) usb nmea usart1 nmea usart2 ubx baud rate (kbaud) 57.6 57.6 input protocol ubx, nmea ubx, nmea, rtcm ubx, nmea, rtcm output protocol nmea nmea ubx messages gga, rmc, gsa, gsv gga, rmc, gsa, gsv nav: sol, svinfo mon: except information messages (ubx inf or nmea txt) user, notice, warning, error user, notice, warning, error user, notice, warning, error
12 4925a?gps?02/06 atr0625 [preliminary] 3.3.4 usb power mode for correct response to the usb host queries, th e device has to know its power mode. this is configured via gpsmode7. if set to bus powered , an upper current limit of 100 ma is reported to the usb host; that is, the device classifies itself as a ?low-power bus-powered function? with no more than one usb power unit load. 3.3.5 active antenna supervisor the two pins p0/nantshort and p15/anton plus one pin of p25/naadet0/miso or p14/naadet1 are always initialized as gener al purpose i/os and used as follows: p15/anton is an output which can be used to switch on and off antenna power supply. input p0/nantshort will indicate an antenna short circuit, i. e. zero dc voltage at the antenna, to the firmware. if the antenna is switched off by output p15/anton, it is assumed that also input p0/nantshort will sign al zero dc voltage, i.e. switch to its active low state. input p25/naadet0/miso or p14/naadet1 will i ndicate a dc current in to the antenna. in case of short circuit, both p0 and p25/p14 will be active, i.e. at low level. if the antenna is switched off by output p15/anton, it is assumed that also input p25/naadet0/miso will signal zero dc current, i.e. switch to its ac tive low state. which pin is used as naadet (p14 or p25) depends on the settings of gpsmode11 and gpsmode10 (see table 3-14 on page 13 ). table 3-12. usb power modes gpsmode7 (reset = pu) description 0 usb device is bus-powered (max. current limit 100 ma) 1 usb device is self-powered (default rom value) table 3-13. pin usage of active antenna supervisor pin usage meaning p0/nantshort nantshort active antenna short circuit detection high = no antenna dc short circuit present low = antenna dc short circuit present p25/naadet0/ miso or p14/naadet1 naadet active antenna detection input high = no active antenna present low = active antenna is present p15/anton anton active antenna power on output high = power supply to active antenna is switched on low = power supply to active antenna is switched off
13 4925a?gps?02/06 atr0625 [preliminary] the antenna supervisor software will be configured as follows: 1. enable control signal 2. enable short circuit detection (power do wn antenna via anton if short is detected via nantshort) 3. enable open circuit detection via naadet the antenna supervisor function may not be disabled by gpsmode pin selection. table 3-14. antenna detection i/o settings gpsmode11 (reset = pu) gpsmode10 (reset = pu) gpsmode8 (reset = pu) location of naadet comment 0 0 0 p25/naadet0/miso 0 0 1 p25/naadet0/miso 0 1 0 p14/naadet1 reserved for further use. do not use this setting. 011 p14/naadet1 (default rom value) 1 0 0 p14/naadet1 reserved for further use. do not use this setting. 1 0 1 p14/naadet1 reserved for further use. do not use this setting. 1 1 0 p25/naadet0/miso 1 1 1 p25/naadet0/miso
14 4925a?gps?02/06 atr0625 [preliminary] 3.4 external connections fo r a working gps system figure 3-2. example of an external connection atr0601 atr0625 sigh sigl sc purf puxto sighi siglo clk23 rf_on see table 3-15 see table 3-15 see table 3-15 see table 3-15 see table 3-15 gnd nc nc nc nc nc nc (see power supply) +3v nc usb_dm usb_dp p18 optional usart 2 optional usart 1 optional usb p31 p21 vddio vdd_usb xt_out xt_in p22 p20 p8 nreset p9 p12 - 17 vbat vbat18 ldo_in ldobat_in vdd18 ldo_out ldo_en nshdn gnd dbg_en tdo ntrst tdi tck tms p23 - 27 p19 p0 - 2 status led timepulse nsleep see table 3-15 p29 - 30 32.368 khz (see rtc) nc: not connected (see power supply) +3v gnd +3v (see power supply) +3v (see power supply)
15 4925a?gps?02/06 atr0625 [preliminary] table 3-15. recommended pin connection pin name recommended external circuit p0/nantshort internal pull-down resistor, leave open if antenna supervision functionality is unused. can be left open if configured as output by user application. p1/gpsmode0 internal pull-down resistor, leave open, in order to disable the gpsmode pin configuration feature. connect to vddio to enable the gpsmode pin configuration f eature. refer to gpsmode definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . can be left open if configured as output by user application. p2/boot_mode internal pull-down resistor, leave open. p8/statusled output in default rom firmware: leave open, only needs pull-up resistor to vddio or pull-down resistor to gnd if used as gpio input by user application an d is not always driven from external sources. p9/extint0 internal pull-up resistor, leave open if unused. p12/gpsmode2/npcs2 internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p13/gpsmode3/ extint1 internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p14/naadet1 internal pull-down resistor, leave open if antenna supervision functionality is unused. can be left open if configured as output by user application. p15/anton internal pull-down resistor, leave open if antenna supervision functionality is unused. can be left open if configured as output by user application. p16/neeprom internal pull-up resistor, leave open if no serial eeprom is connected. otherwise connect to gnd. p17/gpsmode5/sck1 internal pull-down resistor, can be left open if the g psmode feature is not used or configured as output by user application. refer to gp smode definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p18/txd1 output in default rom firmware: leave open if serial interface is not used. p19/gpsmode6/siglo1 internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p20/timepulse/sck2 output in default rom firmware: leave open if timepulse feature is not used. p21/txd2 output in default rom firmware: leave open if serial interface not used. p22/rxd2 internal pull-up resistor, leave open if serial interface is not used. p23/gpsmode7/sck internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p24/gpsmode8/mosi internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p25/naadet0/miso internal pull-down resistor, leave open if antenna supervision functionality is unused. can be left open if configured as output by user application. p26/gpsmode10/nss/ npcs0 internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p27/gpsmode11/npcs1 internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p29/gpsmode12/npcs3 internal pull-up resistor, can be left open if the gpsmode f eature is not used or configured as output by user application. refer to gpsmod e definitions in section ?setting gpsmode0 to gpsmode12? on page 9 . p30/agcout0 internal pull-down resistor, leave open. p31/rxd1 internal pull-up resistor, leave open if serial interface is not used.
16 4925a?gps?02/06 atr0625 [preliminary] 3.4.1 connecting an optional serial eeprom the atr0625 offers the possibilit y to connect an external se rial eeprom. the internal rom firmware supports to store the configuration of the atr0625 in serial eeprom. the pin p16/neeprom signals the firmware that a se rial eeprom is connected with the atr0625. the 32-bit risc processor of the atr0625 accesses the external memory with spi (serial peripheral interface). atmel recommend to use 32 kbit 1.8v serial eeprom, e.g. the atmel at25320ay1-1.8. figure 3-3 shows an example of the serial eeprom connection. figure 3-3. example of a serial eeprom connection note: the gpsmode pin configuration feature c an be disabled, because the configuration can be stored in the serial eeprom. vddi o is the supply voltage for th e pins: p23, p24, p25 and p29. at25320ay1-1.8 atr0625 sck si so cs_n nc gnd gnd hold_n wp_n p23/sck p25/miso/naadet0 p24/mosi p29/npcs3 p16/neeprom p1/gpsmode0 (see power supply) +3v nc: not connected ldo_in ldobat_in vddio vdd18 ldo_out ldo_en nshdn gnd
17 4925a?gps?02/06 atr0625 [preliminary] 4. power supply the baseband ic is supplied with four distinct supply voltages: vdd18, the nominal 1.8v supply voltage for the core, the rf-i/o pins, the memory interface and the test pins and all gpio-pins not mentioned in next item. vddio, the variable supply voltage within 1.8v to 3.6v for following gpio-pins: p1, p2, p8, p12, p14, p16, p17, p18, p19, p20, p21, p23, p24, p25, p2 6, p27 and p29 in input mode, these pins are 5v input tolerant. vdd_usb, the power supply of the usb pins: usb_dm and usb_dp. vbat18 to supply the backup domain: rtc, backup sram and the pins nsleep, nshdn, ldo_en, vbat18, p9/extin0, p13/extint1, p22/rxd2 and p31/rxd1 and the 32khz oscillator. in input mode, the four gpio-pins are 5v input tolerant. figure 4-1 , figure 4-2 , and figure 4-3 show examples of the wiring of atr0625 power supply. figure 4-1. external wiring example using inte rnal ldos and backup power supply atr0625 internal vddusb 0 to 2v or 3v to 3.6v 1.5v to 3.6v 1 f (x7r) ldoout ldoen ldoin ldo18 ldo_in 1 f (x7r) vddio 2.3v to 3.6v ldo_en nshdn vdd18 ldo_out usb sm and transceiver 1.8v to 3.3v variable io domain rtc backup memory core vbat18 vbat vdd ldobat_in ldobat ldobat_in vbat vbat18
18 4925a?gps?02/06 atr0625 [preliminary] the baseband ic contains a built in low dropout voltage regulator ldo18. this regulator can be used if the host system does not provide the core voltage vdd18 of 1.8v nominal. in such case, ldo18 will provide a 1.8v supply voltage from any input voltage vdd between 2.3v and 3.6v. the ldo_en input can be used to shut down vdd18 if the system is in standby mode. if the host system does however supply a 1.8v core voltage directly, this voltage has to be connected to the vdd18 supply pins of t he baseband ic. ldo_en must be connected to gnd. ldo_in can be connected to gnd. ldo_out must not be connected. a second built in low dropout voltage regulator ldobat provides the supply voltage for the rtc and backup sram from any input voltage ldobat_in between 2.3v and 3.6v or from vbat between 1.5v and 3.6v. the backup battery connected to vbat is only discharged if the supply connected to ldobat_in is shut-down. only after vdd18 has been supplie d to atr0625 the rtc section will be initialized properly. if only vbat is applied first, the current c onsumption of the rtc and backup sram is undetermined. figure 4-2. external wiring example using 1.8v from host system and backup power supply atr0625 internal vddusb 0 to 2v or 3v to 3.6v 1.5v to 3.6v 1 f (x7r) ldoout ldoen ldoin ldo18 ldo_in 1 f (x7r) vddio ldo_en vdd18 ldo_out usb sm and transceiver 1.8v to 3.3v variable io domain rtc backup memory core vbat18 vbat vdd ldobat_in ldobat ldobat_in vbat vbat18 2.3v to 3.6v 1.65v to 1.95v
19 4925a?gps?02/06 atr0625 [preliminary] the usb transceiver is disabled if vdd_usb < 2.0v. in this case the pins usb_dm and usb_dp are connected to gnd (internal pull-down resistors). the usb transceiver is enabled if vdd_usb within 3.0v and 3.6v. figure 4-3. external wiring example using internal ldos , usb supply voltage and backup power supply atr0625 internal usb-vsb 5v vddusb 1.5v to 3.6v 1 f (x7r) ldoout ldoen ldoin ldo18 ldo_in 1 f (x7r) vddio ldo_en nshdn vdd18 external ldo 3.3v ldo_out usb sm and transceiver 1.8v to 3.3v variable io domain rtc backup memory core vbat18 vbat vdd ldobat_in ldobat ldobat_in vbat vbat18
20 4925a?gps?02/06 atr0625 [preliminary] 5. oscillator figure 5-1. crystal connection xt_in xt_out rtc atr0625 internal 32 khz crystal oscillator 32.768 khz clock 32.768 khz 50 ppm max. 25 pf max. 25 pf 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters pin symbol min. max. unit operating free air temperature range ?40 +85 c storage temperature ?60 +150 c dc supply voltage vdd18 ?0.3 +1.95 v dc supply voltage vddio ?0.3 +3.6 v dc supply voltage vdd_usb ?0.3 +3.6 v dc supply voltage ldo_in ?0.3 +3.6 v dc supply voltage ldobat_in ?0.3 +3.6 v dc supply voltage vbat ?0.3 +3.6 v dc input voltage p0, p15, p30, sighi, siglo, clk23, xt_in, tms, tck, tdi, ntrst, dbg_en, ldo_en, nreset ?0.3 +1.95 v dc input voltage usb_dm, usb_dp ?0.3 +3.6 v dc input voltage p1, p2, p8, p9, p12 to p14, p16 to p27, p29, p31 ?0.3 +5.0 v note: minimum/maximum limits are at +25c ambi ent temperature, unless otherwise specified
21 4925a?gps?02/06 atr0625 [preliminary] 7. electrical characteristics if no additional information is given in column test conditio ns, the values apply to a temperature range from ?40c to +85c. no. parameters test conditio ns pin symbol min. typ. max. unit 1.1 dc supply voltage core vdd18 vdd18 1.65 1.8 1.95 v 1.2 dc supply voltage vddio domain (1) vddio vddio 1.65 1.8/3.3 3.6 v 1.3 dc supply voltage usb (2) vdd_usb vddusb 3.0 3.3 3.6 v 1.4 dc supply voltage backup domain (3) vbat18 vbat18 1.65 1.8 3.6 v 1.5 dc output voltage vdd18 v o,18 0 vdd18 v 1.6 dc output voltage vddio v o,io 0vddiov 1.7 low-level input voltage vdd18 domain vdd18 = 1.65v to 1.95v v il,18 ?0.3 0.3 vdd18 v 1.8 high-level input voltage vdd18 domain vdd18 = 1.65v to 1.95v v ih,18 0.7 vdd18 vdd18 + 0.3 v 1.9 low-level input voltage vddio domain vddio = 1.65v to 3.6v v il,io ?0.3 +0.41 v 1.10 high-level input voltage vddio domain vddio = 1.65v to 3.6v v ih,io 1.46 5.0 v 1.11 low-level input voltage vbat18 domain vbat18 = 1.65v to 1.95v p9, p13, p22, p31 v il,bat ?0.3 +0.41 v 1.12 high-level input voltage vbat18 domain vbat18 = 1.65v to 1.95v p9, p13, p22, p31 v ih,bat 1.46 5.0 v 1.13 low-level input voltage usb vdd_usb = 3.0v to 3.6v dp, dm v il,usb ?0.3 +0.8 v 1.14 high-level input voltage usb vdd_usb = 3.0v to 3.6v dp, dm v ih,usb 2.0 4.6 v 1.15 low-level output voltage vdd18 domain i ol = 1.5 ma, vdd18 = 1.65v v ol,18 0.4 v 1.16 high-level output voltage vdd18 domain i oh = ?1.5 ma, vdd18 = 1.65v v oh,18 vdd18 ? 0.45 v 1.17 low-level output voltage vddio domain i ol = 1.5 ma, vddio = 3.0v v ol,io 0.4 v 1.18 high-level output voltage vddio domain i oh = ?1.5 ma, vddio = 3.0v v oh,io vddio ? 0.5 v 1.19 low-level output voltage vbat18 domain i ol = 1 ma p9, p13, p22, p31 v ol,bat 0.4 v 1.20 high-level output voltage vbat18 domain i oh = ?1 ma p9, p13, p22, p31 v oh,bat 1.2 v 1.21 low-level output voltage usb i ol = 1.5 ma, vdd_usb = 3.0v to 3.6v, 27 ? external series resistor dp, dm v ol,usb 0.4 v 1.22 high-level output voltage usb i oh = ?1.5 ma, vdd_usb = 3.0v to 3.6v, 27 ? external series resistor dp, dm v oh,usb 2.7 v notes: 1. vddio is the supply voltage for the following gpio pins: p1, p2, p8, p12, p14, p16, p17, p1 8, p19, p20, p21, p23, p24, p25, p26, p27 and p29 2. values defined for operating the usb interface. otherwise vdd_usb may be connected to ground 3. supply voltage vbat18 for backup domain is generated internally by the ldobat
22 4925a?gps?02/06 atr0625 [preliminary] 1.23 input-leakage current (standard inputs and i/os) vdd18 = 1.95v v il = 0v i leak ?1 +1 a 1.24 input capacitance i cap 10 pf 1.25 input pull-up resistor nreset r pu 0.7 1.6 k ? 1.26 input pull-up resistor tck, tdi, tms r pu 10 30 k ? 1.27 input pull-up resistor p9, p13, p22, p31 r pu 100 220 k ? 1.28 input pull-down resistor dbg_en, ntrst, r pd 10 30 k ? 1.29 input pull-down resistor rf_on, p0, p15, p30 r pd 100 220 k ? 1.30 configurable input pull-up resistor p1, p2, p8, p12, p14, p[16-21], p[23-27], p29 r cpu 62 330 k ? 1.31 configurable input pull-down resistor p1, p2, p8, p12, p14, p[16-21], p[23-27], p29 r cpd 45 160 k ? 1.32 configurable input pull-up resistor (idle state) usb_dp r cpu 0.9 1.575 k ? 1.33 configurable input pull-up resistor (operation state) usb_dp r cpu 1.425 3.09 k ? 1.34 input pull-down resistor usb_dp usb_dm r pd 10 500 k ? 7. electrical characteristics (continued) if no additional information is given in column test conditio ns, the values apply to a temperature range from ?40c to +85c. no. parameters test conditio ns pin symbol min. typ. max. unit notes: 1. vddio is the supply voltage for the following gpio pins: p1, p2, p8, p12, p14, p16, p17, p1 8, p19, p20, p21, p23, p24, p25, p26, p27 and p29 2. values defined for operating the usb interface. otherwise vdd_usb may be connected to ground 3. supply voltage vbat18 for backup domain is generated internally by the ldobat
23 4925a?gps?02/06 atr0625 [preliminary] 9. esd sensitivity the atr0625 is an esd sensitive device. the current esd values are to be defined. observe precautions for handling 10. ldo18 the ldo18 is a built in low dropout voltage regulator which can be used if the host system does not provide the core voltage vdd18. 8. power consumption mode conditions typ. unit sleep at 1.8v, no clk23 0.065 (1) ma shutdown rtc, backup sram and ldobat 0.007 (1) normal satellite acquisition 25 normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 ma 14 all channels disabled 11 note: 1. specified value only table 10-1. electrical characteristics of ldo18 parameter conditions min. typ. max. unit supply voltage ldo_in 2.3 3.6 v output voltage (ldo_out) 1.65 1.8 1.95 v output current (ldo_out) 80 ma current consumption after startup, no load, at room temperature 80 a current consumption standby mode (ldo_en = 0), at room temperature 15 a
24 4925a?gps?02/06 atr0625 [preliminary] 11. ldobat and backup domain the ldobat is a built in low dropout volta ge regulator which provides the supply voltage vbat18 for the rtc, backup sram, p9, p13, p22, p31, nsleep and nshdn. the ldobat voltage regulator switches in battery mode if ldobat_in falls below 1.5v. table 11-1. electrical characteristics of ldobat parameter conditions min. typ. max. unit supply voltage ldobat_in 2.3 3.6 v supply voltage vbat 1.5 3.6 v output voltage (vbat18) if switch connects to ldobat_in. 1.65 1.8 1.95 v output current (vbat18) 1.5 ma current consumption ldobat_in (1) after startup (sleep/backup mode), at room temperature 15 a current consumption vbat (1) after startup (backup mode and ldobat_in = 0v), at room temperature 10 a current consumption after startup (norma l mode), at room temperature 1.5 ma note: 1. if no current is caused by outputs (pad ou tput current as well as current across internal pull-up resistors)
25 4925a?gps?02/06 atr0625 [preliminary] 13. package qfn56 12. ordering information extended type number package mpq remarks atr0625-pyqw qfn56 2000 8 mm 8 mm, 0.50 mm pitch, pb-free, rohs-compliant, green atr0625-ek1 - 1 evaluation kit/road test kit ATR0625-DK1 - 1 development kit inclusive example design information specifications according to din technical drawings package: qfn56 8 x 8 exposed pad 6.5 x 6.5 0.25 0.4 0.1 0.9 max. 8 0.5 nom. 6.5 pin 1 id 14 56 1 29 42 43 56 28 15 14 1 issue: 1; 02.09.05 drawing-no.: 6.543-5121.01-4 dimensions in mm not indicated tolerances 0.05 0.05 -0.05 +0
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